R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1008
R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Quantity
Price
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Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
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Manufacturer:
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Section 16 Serial Communication Interface (SCI, IrDA, CRC)
16.9
16.9.1
Table 16.13 shows the interrupt sources in serial communication interface mode. A different
interrupt vector is assigned to each interrupt source, and individual interrupt sources can be
enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC or
DMAC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is
performed by the DTC or DMAC. When the RDRF flag in SSR is set to 1, an RXI interrupt
request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt
request is generated. An RXI interrupt request can activate the DTC or DMAC to perform data
transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC
or DMAC. A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to
1. If a TEI interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has
priority for acceptance. However, note that if the TDRE and TEND flags are cleared
simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine
later.
Page 978 of 1448
Interrupt Sources
SCI Normal Mode
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
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