R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 192

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 7 Bus Controller (BSC)
7.3.1
ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.
Note:
7.3.2
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.
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Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
*
Bit Name
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
Bit Name
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
Bus Width Control Register (ABWCR)
Access State Control Register (ASTCR)
In modes 2 and 4, ABWCR is initialized to 1. In modes 1, 3, 5, and 7, ABWCR is
initialized to 0.
Initial Value*
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Initial Value
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Area 7 to 0 Bus Width Control
These bits select whether the corresponding
area is to be designated as 8-bit access space
or 16-bit access space.
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
Description
Area 7 to 0 Access State Control
These bits select whether the corresponding
area is to be designated as 2-state access
space or 3-state access space. Wait state
insertion is enabled or disabled at the same
time.
0: Area n is designated as 2-state access
1: Area n is designated as 3-state access
(n = 7 to 0)
space
Wait state insertion in area n access is
disabled
space
Wait state insertion in area n access is
enabled
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
(n = 7 to 0)
Jul 22, 2010