R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 531

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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H8S/2427, H8S/2427R, H8S/2425 Group
10.2
DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a
set of register information that is stored in an on-chip RAM to the corresponding DTC registers
and transfers data. After the data transfer, it writes a set of updated register information back to the
RAM.
• DTC enable registers A to I (DTCERA to DTCERI)
• DTC vector register (DTVECR)
• DTC vector base register (DTCVBR)
• DTC control register (DTCCR)
10.2.1
MRA selects the DTC operating mode.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7
6
Bit Name
SM1
SM0
Register Descriptions
DTC Mode Register A (MRA)
Initial Value
Undefined
Undefined
R/W
Description
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0x: SAR is fixed
10: SAR is incremented after a transfer
11: SAR is decremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
(by –1 when Sz = 0; by –2 when Sz = 1)
Section 10 Data Transfer Controller (DTC)
Page 501 of 1448

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