R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 226
R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 Bus Controller (BSC)
(3)
In externally expanded mode, areas 2 to 5 are all external address space.
When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.
The basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for the
memory interface of areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS2
to RAS5 signals, respectively.
If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM
can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM
space.
If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64-
Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are
used as the RAS, CAS, WE, and SDRAMφ signals for the continuous synchronous DRAM space,
respectively. The OE pin is used as the CKE signal.
(4)
In externally expanded mode, all of area 6 is external space.
When area 6 external space is accessed, the CS6 signal can be output.
Either the basic bus interface or address/data multiplexed I/O interface can be used for the
memory interface of area 6.
(5)
Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode, the space
excluding the on-chip RAM and internal I/O registers is external address space. The on-chip RAM
is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external address space.
When area 7 external address space is accessed, the CS7 signal can be output.
Either the basic bus interface or address/data multiplexed I/O interface can be used for the
memory interface of area 7.
Page 196 of 1448
Areas 2 to 5
Area 6
Area 7
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
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