R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 419

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
Transfer requests (activation sources) are external requests and auto-requests. With auto-requests,
the DMAC is only activated by register setting, and the specified number of transfers are
performed automatically. With auto-requests, cycle steal mode or burst mode can be selected. In
cycle steal mode, the bus is released to another bus master each time a transfer is performed. In
burst mode, the bus is held continuously until transfer ends.
Figures 8.15 and 8.16 show an example of the setting procedure for normal mode in common
register enabled mode and common register disabled mode, respectively.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Set number of transfers
Set transfer source and
Normal mode setting
transfer destination
Figure 8.15 Example of Normal Mode Setting Procedure
Set MDLCFGCR
Read DMABCRL
Set DMABCRH
Set DMABCRL
Set DMACRF
Normal mode
Set DRSEL
addresses
(Common Register Enabled Mode)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[1] Set the DMCOMMD bit in MDLCFGCR to 1.
[2] Set RSEL4 or RSEL5 bit in DRSEL to 1 depending on the
[3] Set each bit in DMABCRH.
[4] Set the transfer source address in SAR and transfer
[5] Set the number of transfers in ETCRA.
[6] Set each bit in DMACRF.
[7] Read DTE = 0 and DTME = 0 in DMABCRL.
[8] Set each bit in DMABCRL.
channel to be set.
destination address in DAR.
•
•
• Specify enabling or disabling of internal interrupt
• Set the transfer data size with the DTSZ bit.
• Specify whether SAR is to be incremented,
• Clear the BLKE bit to 0 to select normal mode.
• Specify whether DAR is to be incremented,
• Select the activation source with bits DTF3 to DTF0.
clearing with the DTA bit.
decremented, or fixed, with the SAID and SAIDE bits.
decremented, or fixed, with the DAID and DAIDE bits.
with DTIE bit.
Specify enabling or disabling of transfer end interrupts
Set the DTE bit to 1 to enable transfer.
Section 8 DMA Controller (DMAC)
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