R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 207
R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
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H8S/2427, H8S/2427R, H8S/2425 Group
7.3.9
DRAMCR is used to make DRAM/synchronous DRAM interface settings.
Note: The synchronous DRAM interface is not supported by the H8S/2427 Group and H8S/2425
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
15
14
13
Group. The DRAM interface is not supported by the 5-V version.
Bit Name
OEE
RAST
⎯
DRAM Control Register (DRAMCR)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
OE Output Enable
The OE signal used when EDO page mode DRAM
is connected can be output. The OE signal is
common to all areas designated as DRAM space.
When the synchronous DRAM is connected, the
CKE signal can be output. The CKE signal is
common to the continuous synchronous DRAM
space.
0: OE/CKE signal output disabled
1: OE/CKE signal output enabled
RAS Assertion Timing Select
Selects whether, in DRAM access, the RAS signal
is asserted from the start of the T
edge of φ) or from the falling edge of φ.
Figure 7.4 shows the relationship between the
RAST bit setting and the RAS assertion timing.
The setting of this bit applies to all areas
designated as DRAM space.
0: RAS is asserted from φ falling edge in T
1: RAS is asserted from start of T
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
OE/CKE pin can be used as I/O port
Section 7 Bus Controller (BSC)
r
r
cycle (rising
cycle
Page 177 of 1448
r
cycle
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