R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 739

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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H8S/2427, H8S/2427R, H8S/2425 Group
11.15.2 Port G Data Register (PGDR)
PGDR stores output data for the port G pins.
11.15.3 Port G Register (PORTG)
PORTG shows the pin states of port G. PORTG cannot be modified.
Note:
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
Bit Name
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PG6DR
PG5DR
PG4DR
PG3DR
PG2DR
PG1DR
PG0DR
*
Determined by the states of pins PG6 to PG0.
Initial Value
Undefined
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
If this bit is read, it will return an undefined value.
If this register is read while a PGDDR bit is set to 1,
the corresponding PGDR value is read. If this
register is read while a PGDDR bit is cleared to 0,
the corresponding pin state is read.
Description
Reserved
This bit is always read as 0, and cannot be
modified.
Output data for a pin is stored when the pin
function is specified as a general purpose I/O.
Section 11 I/O Ports
Page 709 of 1448

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