R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 529

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
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Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
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H8S/2427, H8S/2427R, H8S/2425 Group
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 10.1 shows a block diagram of the DTC.
10.1
• Transfer possible over any number of channels
• Three transfer modes
1. Normal mode
2. Repeat mode
3. Block transfer mode
• One activation source can trigger a number of data transfers (chain transfer)
• Direct specification of 16-Mbyte address space possible
• Activation by software is possible
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Read skip of the transfer information can be specified
• Writeback skip is executed for the fixed transfer source and destination addresses
• Module stop state can be set
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
From 1 to 65,536 transfers can be specified.
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
Once the specified number of transfers (1 to 256) has ended, the initial state is restored, and
transfer is repeated.
One operation transfers one block of data.
The block size is 1 to 256 bytes or words.
From 1 to 65,536 transfers can be specified.
Either the transfer source or the transfer destination is designated as a block area.
Features
Section 10 Data Transfer Controller (DTC)
Section 10 Data Transfer Controller (DTC)
Page 499 of 1448

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