R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1000

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 16 Serial Communication Interface (SCI, IrDA, CRC)
16.7.7
Data reception in Smart Card interface mode uses the same operation procedure as for normal
serial communication interface mode. Figure 16.29 illustrates the retransfer operation when the
SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SSR is
2. The RDRF bit in SSR is not set for a frame in which an error has occurred.
3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
4. The receive operation is judged to have been completed normally, and the RDRF flag in SSR
Figure 16.30 shows a flowchart for reception. The sequence of receive operations can be
performed automatically by specifying the DTC or DMAC to be activated with an RXI interrupt
source. In a receive operation, an RXI interrupt request will be generated if the RIE bit is 1 when
the RDRF flag in SSR is set to 1. If the RXI interrupt request is designated beforehand as a DTC
or DMAC activation source, the DTC or DMAC will be activated by the RXI interrupt request,
and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically
when data transfer is performed by the DTC or DMAC. If an error occurs in receive mode and the
ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated, and so the
error flag must be cleared to 0. In the event of an error, the DTC or DMAC is not activated and
receive data is skipped. Therefore, receive data is transferred for only the specified number of
bytes in the event of an error. Even when a parity error occurs in receive mode and the PER flag is
set to 1, the data that has been received is transferred to RDR and can be read from there.
Note: For details on receive operations in block transfer mode, refer to section 16.4, Operation in
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automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is
generated. The PER bit in SSR should be cleared to 0 before the next parity bit is sampled.
is automatically set to 1. If the RIE bit in SCR is set at this time, an RXI interrupt request is
generated.
Asynchronous Mode.
Serial Data Reception (Except for Block Transfer Mode)
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010