R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 787

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
12.3.2
TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR
registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7
6
5
4
3
2
1
0
Bit Name
⎯
⎯
BFB
BFA
MD3
MD2
MD1
MD0
Timer Mode Register (TMDR)
0
0
Initial Value
1
1
0
0
0
0
R/W
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Buffer Operation B
Specifies whether TGRB is to operate in the
normal way, or TGRB and TGRD are to be used
together for buffer operation. When TGRD is used
as a buffer register, TGRD input capture/output
compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD,
bit 5 is reserved. It is always read as 0 and cannot
be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer
Buffer Operation A
Specifies whether TGRA is to operate in the
normal way, or TGRA and TGRC are to be used
together for buffer operation. When TGRC is used
as a buffer register, TGRC input capture/output
compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC,
bit 4 is reserved. It is always read as 0 and cannot
be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer
Modes 3 to 0
These bits are used to set the timer operating
mode.
MD3 is a reserved bit. The write value should
always be 0. See table 12.12 for details.
operation
operation
Section 12 16-Bit Timer Pulse Unit (TPU)
Page 757 of 1448