R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 921

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
15.3.3
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by overflows.
Note:
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7
6
5
4 to 0
*
Bit Name
WOVF
RSTE
⎯
⎯
Reset Control/Status Register (RSTCSR)
Only 0 can be written, to clear the flag.
Initial Value
0
0
0
All 1
R/W
R/(W) *
R/W
R/W
⎯
Description
Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be written.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1,
and then writing 0 to WOVF
Reset Enable
Specifies whether or not a reset signal is
generated in the chip if TCNT overflows during
watchdog timer operation.
0: Reset signal is not generated even if TCNT
1: Reset signal is generated if TCNT overflows
Reserved
Can be read and written, but does not affect
operation.
Reserved
These bits are always read as 1 and cannot be
modified.
overflows
(Though this LSI is not reset, TCNT and TCSR
in WDT are reset)
Section 15 Watchdog Timer (WDT)
Page 891 of 1448