R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 26

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 19 D/A Converter ...............................................................................1067
19.1 Features............................................................................................................................ 1067
19.2 Input/Output Pins............................................................................................................. 1069
19.3 Register Descriptions ....................................................................................................... 1069
19.4 Operation ......................................................................................................................... 1072
19.5 Usage Notes ..................................................................................................................... 1074
Section 20 Synchronous Serial Communication Unit (SSU) .......................... 1075
20.1 Features............................................................................................................................ 1075
20.2 Input/Output Pins............................................................................................................. 1077
20.3 Register Descriptions ....................................................................................................... 1078
20.4 Operation ......................................................................................................................... 1091
20.5 Interrupt Requests ............................................................................................................ 1114
20.6 Usage Note....................................................................................................................... 1115
Section 21 FSI Interface ..................................................................................1117
21.1 Features............................................................................................................................ 1117
21.2 Input/Output Pins............................................................................................................. 1118
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19.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)........................................... 1069
19.3.2 D/A Control Register 23 (DACR23) .................................................................. 1070
19.5.1 Module Stop Function Setting ............................................................................ 1074
19.5.2 D/A Output Hold Function in Software Standby Mode...................................... 1074
20.3.1 SS Control Register H (SSCRH) ........................................................................ 1079
20.3.2 SS Control Register L (SSCRL) ......................................................................... 1081
20.3.3 SS Mode Register (SSMR) ................................................................................. 1082
20.3.4 SS Enable Register (SSER) ................................................................................ 1083
20.3.5 SS Status Register (SSSR).................................................................................. 1084
20.3.6 SS Control Register 2 (SSCR2) .......................................................................... 1087
20.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................. 1089
20.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................. 1090
20.3.9 SS Shift Register (SSTRSR)............................................................................... 1090
20.4.1 Transfer Clock .................................................................................................... 1091
20.4.2 Relationship of Clock Phase, Polarity, and Data ................................................ 1091
20.4.3 Relationship between Data Input/Output Pins and Shift Register ...................... 1092
20.4.4 Communication Modes and Pin Functions ......................................................... 1093
20.4.5 SSU Mode........................................................................................................... 1095
20.4.6 SCS Pin Control and Conflict Error.................................................................... 1106
20.4.7 Clock Synchronous Communication Mode ........................................................ 1107
20.6.1 Module Stop Function Setting ............................................................................ 1115