R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 390

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 8 DMA Controller (DMAC)
Page 360 of 1448
Bit
4
3
Bit Name
DTE4
DMIE5
Initial
Value
0
0
R/W
R/W
R/W
Data Transfer Enable 4
Description
Enables or disables DMA transfer for the activation
source selected by the DTF3 to DTF0 bits in
DMACRS.
When DTE4 = 0, data transfer is disabled and the
activation source is ignored. If the activation source
is an internal interrupt, an interrupt request is
issued to the CPU or DTC. If the DTE4 bit is
cleared to 0 when DTIE0 = 1, the DMAC regards
this as indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
When DTE4 = 1 and DTME4 = 1, data transfer is
enabled and the DMAC waits for a request by the
activation source. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
•
•
•
[Setting condition]
•
Data Transfer Interrupt Enable 5
Enables or disables an interrupt to the CPU or DTC
when transfer on channel 5 has been interrupted. If
the DTME5 bit is cleared to 0 when DMIE5 = 1, the
DMAC regards this as indicating the break in a
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either by
clearing the DMIE5 bit to 0 in the interrupt handling
routine, or by performing processing to continue
transfer by setting the DTME5 bit to 1.
When initialization is performed
When the specified number of transfers have
been completed
When 0 is written to the DTE4 bit to forcibly
suspend the transfer, or for a similar reason
When 1 is written to the DTE4 bit after reading
DTE4 = 0
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010