R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 605

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
• P12/TEND0/TEND1/TEND4/PO10/TIOCC0/TCLKA
[Legend]
x:
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
DMAC settings
TPU channel 0
settings
P12DDR
NDER10
Pin function
TPU channel 0
settings
MD3 to MD0
IOC3 to IOC0
CCLR2 to
CCLR0
Output function
The pin function is switched as shown below according to the combination of bit DMCOMMD
in MDLCFGCR, bits RSEL4, RSEL1, and RSEL0 in DRSEL, bit TEE0 in DMATCR, bit TEE
in DMAECRS0, and bit TEE in DMAECRF4 of the DMAC, TPU channel 0 settings (by bits
MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in
TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH and bit
DMASEL0 in PFCR3 of the PPG, and bit P12DDR.
Don't care
2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100.
3. TIOCD0 output disabled. Output disabled and settings (2) effective when BFA = 1 or
TCLKA input when phase counting mode is set for channels 1 and 5.
BFB = 1 in TMDR_0.
(1) in table
TIOCC0
output
B'0000,
B'0100,
below
B'1xxx
⎯
⎯
(2)
⎯
⎯
B'0000
P12 input
(1) in table below
B'0001 to
B'0101 to
compare
⎯
B'0011,
B'0111
Output
0
output
(1)
⎯
(2) in table below
output
P12
0
B'001x
B'xx00
(2)
⎯
⎯
TCLKA input*
1
output
PO10
TIOCC0 input*
1
Other than
mode 1
PWM*
B'0010
B'xx00
output
(1)
⎯
(2) in table
2
TEND0
output
below
3
⎯
⎯
⎯
1
PWM mode
Other than
2 output
B'101
(3) in table
Other than B'xx00
(1)
TEND1
output
below
⎯
⎯
⎯
B'0011
Section 11 I/O Ports
Page 575 of 1448
(4) in table
B'101
TEND4
output
below
(2)
⎯
⎯
⎯
⎯