R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 511
R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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H8S/2427, H8S/2427R, H8S/2425 Group
(2)
When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three
cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is
satisfied.
If the EBRE bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another
bus master.
Transfer requests for other channels are held pending until the end of transfer on the current
channel.
Figures 9.31 to 9.34 show operation timing examples for various conditions.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
φ pin
Bus cycle
CPU
operation
ETEND
EDA bit
Auto Request/Burst Mode/Normal Transfer Mode
CPU cycle CPU cycle
External
1
space
Figure 9.31 Auto Request/Burst Mode/Normal Transfer Mode
External
space
(CPU Cycles/Dual Address Mode/EBRE = 0)
EXDMA
External
space
read
EXDMA
write
EXDMA
read
EXDMA
write
Repeated
Section 9 EXDMA Controller (EXDMAC)
Last transfer cycle
EXDMA
read
EXDMA
write
Page 481 of 1448
CPU cycle
0
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