TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 98

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

MASTERCLK
MASTERCLK
Table 6.1.2 Relationship Among Different Clock Frequencies (for TMPR4937XBG-300, CPUCLK = 266 MHz)
Table 6.1.3 Relationship Among Different Clock Frequencies (for TMPR4937XBG-300, CPUCLK = 300 MHz)
and Boot Configured
Master Clock (Input)
Master Clock (Input)
and Boot Configured
106.4
(MHz)
33.3
26.6
88.7
22.2
66.5
16.6
59.1
14.8
120
100
(MHz)
133
30
25
75
18
66
16
† The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10].
† The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10].
-
-
Settings
Settings
Boot
Configured
Setting
ADDR[3:0]
HLHL (x10.0)
HLLH (x12.0)
LLHH (x18.0)
Boot
Configured
Setting
ADDR[3:0]
HLLL (x16.0)
HLHL (×10.0)
HLLH (×12.0)
LLHH (×18.0)
HHHL (x2.5)
HHLH (x3.0)
HHHH (×2.0)
HLLL (×16.0)
HHHH(x2.0)
HLHH(x8.0)
HHLL (x4.0)
LHHH(x4.5)
HLHH (×8.0)
HHHL (×2.5)
HHLH (×3.0)
LHHH (×4.5)
HHLL (×4.0)
CPUCLK
CPUCLK
(MHz)
300
(MHz)
266
Internal Clock
Internal Clock
GBUSCLK
GBUSCLK
106.4
(MHz)
120
100
88.7
66.5
59.1
(MHz)
133
75
66
-
IMBUSCLK
IMBUSCLK
33.2
29.6
(MHz)
(MHz)
60
50
37
33
66
53
44
-
SDCLK
[3:0]
(MHz)
106.4 106.4
SDCLK
[3:0]
(MHz)
120
100
88.7
66.5
59.1
133
75
66
-
120
100
88.7
66.5
59.1
133
(1/1)
75
66
(1/1)
HH
HH
Boot Configured Settings
-
Boot Configured Settings
SYSCLK (MHz)
SYSCLK (MHz)
6-4
PCIDIVMODE[2:0]
PCIDIVMODE[2:0]
44.3 29.6 22.2
33.3 22.2 16.6
29.6 19.7 14.8
(1/2)
60
50
37
33
(1/2)
HL
66
53
HL
-
44.3 33.3
35.5 26.6
(1/3)
40
33
25
22
(1/3)
LH
LH
-
External Clock (Output)
External Clock (Output)
(1/4)
30
25
18
16
(1/4)
LL
LL
-
66.5
(1/4)
LLH
75
(1/4)
LLH
-
(1/4.5)
59.1
(1/4.5)
LHH
66
LHH
-
Chapter 6 Clocks
53.2
PCICLK[5:0] (MHz) †
HLH
(1/5)
PCICLK[5:0] (MHz) †
60
HLH
(1/5)
PCIDIVMODE[2:0]
-
PCIDIVMODE[2:0]
CCFG Settings
CCFG Settings
(1/5.5)
48.4
(1/5.5)
HHH
HHH
54
-
33.3 29.6 26.6 24.2
(1/8)
LLL
37
(1/8)
LLL
-
(1/9)
LHL
33
(1/9)
LHL
-
(1/10)
(1/10)
HLL
30
HLL
-
(1/11)
(1/11)
HHL
27
HHL
-