TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 124

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

7.5
Timing Diagrams
(1) The clock frequency of the SYSCLK signal can be set to one of the following divisions of the internal
(2) Both the BWE* signal and BE* signal are indicated in all timing diagrams. The setting of the Channel
(3) All Burst cycles in the timing diagrams illustrate examples in which the address increases by increments
(4) The timing diagrams display each clock cycle currently being accessed using the symbols described in
(5) Shaded areas (
Please take the following points into account when referring to the timing diagrams.
bus clock (GBUSCLK): 1/1, 1/2, 1/3, or 1/4. Also, the operating reference clock frequency can be set to
one of the following divisions of the internal bus clock (GBUSCLK) for each channel: 1/1, 1/2, 1/3, or
1/4. (See 7.3.8.) The timing diagrams indicate the SYSCLK signal clock frequency and channel
operating reference clock frequency as being equivalent.
Control Register (EBCCRn) determines whether the BWE* pin will function as BWE* or BE*.
of 1 starting from 0. However, cases where the CWF (Critical Word First) function of the TX49 core
was used or the decrement burst function performed by the DMA Controller was used are exceptions.
the following table.
SWn
PWn
ASn
CSn
AHn
CHn
ESn
ACEn
Sn
Normal Wait Cycles
Page Wait Cycles
Set-up Time from SHWT Address Validation to CE Fall
Set-up Time from SHWT CE Fall to OE/SWE Fall
Hold Time from SHWT CE Rise to Address Change
Hold Time from SHWT OE/SWE Rise to CE Rise
Synch Cycles of the External Input Signal
Address Clock Enable Cycles
Other Cycles
) in the diagrams are undefined values.
7-24
Chapter 7 External Bus Controller