TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 181

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

63:32
31:28
27:24
23:21
20:14
13:11
10:8
Bit
7
8.4.1
15
63
47
31
Mnemonic
FIFVC
EIS[3:0]
DIS[3:0]
FIFWP
FIFVC
FIFRP
RSFIF
14
EIS[3:0]
DMA Master Control Register (DM0MCR, DM1MCR)
0000
R
Offset address: DMAC0 0xB150, DMAC1 0xB950
This register controls the entire DMA Controller.
13
Reserved
Error Interrupt
Status
Normal
Completion
Interrupt Status
Reserved
FIFO Valid Entry
Count
FIFO Write
Pointer
FIFO Read
Pointer
Reset FIFO
Field Name
FIFWP
000
28
R
Figure 8.4.1 DMA Master Control Register (1/2)
27
11
Error Interrupt Status [3:0] (Default: 0x0)
These four bits indicate the error interrupt status of each channel. EIS[n]
corresponds to channel n.
1: There is an error interrupt in the corresponding channel.
0: There is no error interrupt in the corresponding channel.
Done Interrupt Status [3:0] (Default: 0x0)
These four bits indicate the transfer completion (transfer complete or chain
ended) interrupt status of each channel. DIS[n] corresponds to channel n.
1: There is a transfer completion interrupt in the corresponding channel.
0: There is no transfer completion interrupt in the corresponding channel.
FIFO Valid Entry Count (Default: 0000000)
These read only bits indicate the byte count of data that were written to
FIFO but not read out from the FIFO.
FIFO Write Pointer (Default: 000)
These read only bits indicate the next write position in FIFO. This is a
diagnostic function.
FIFO Read Pointer (Default: 000)
These read only bits indicate the next read position in FIFO. This is a
diagnostic function.
Reset FIFO (Default: 0)
This bit is used for resetting FIFO. When this bit is set to “1”, the FIFO read
pointer, FIFO write pointer and FIFO valid entry count are initialized to “0”.
If an error occurs during DMA transfer, use this bit when data remains in
the FIFO (when the FIFO Valid entry Count Field is not “0”) to initialize the
FIFO.
10
DIS[3:0]
0000
R
FIFRP
000
R
24
Reserved
Reserved
8
8-25
RSFIF
R/W
23
7
0
Reserved
Description
6
Chapter 8 DMA Controller
FIFUM[3:0]
21
0000
R/W
20
3
0000000
Reserved
FIFVC
R
2
RRPT MSTEN
R/W
1
0
Read/Write
R
R
R
R
R
R/W
R/W
48
32
16
0
0
⎯
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value