TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 69

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

4.
4.1
Address Mapping
of mapping to a physical address from the virtual address of TX49/H3 core.
This chapter explains the physical address map of TX4937.
Please refer to "64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture" about the details
TX4937 Physical Address Map
each controller for the details of the mapping.
vectors are allocated shown as Figure 4.1.1. Usually ROM connected to the external bus controller channel 0
is used for the memory device that stores the reset vectors. TX4937 also supports using the memories on PCI
bus as the memory device stores the reset vectors. Refer to “10.3.12 PCI Boot Configuration” for detail
about this.
allocate resources of TX4937 to the PCI bus address space, refer to §10.3.5 Target Access.
TX4937 supports up to 64G (2
Following resources are to be allocated in the physical address of the TX4937.
Each resource is to be allocated in any physical addresses by the register setup. Refer to the explanation of
At initialization, only the internal registers and the memory space which stores the TX49/H3 core reset
It is possible to access a resource of TX4937 as a PCI target device through PCI bus. About how to
•
•
•
•
TX4937 Internal registers (refer to “4.2 Register Map”)
SDRAM (refer to “9.3.2 Address Mapping”)
External Devices such as ROM, I/O Devices (refer to “7.3.3 Address Mapping”)
PCI Bus (refer to “10.3.4 Initiator Access”)
0xF_FFFF_FFFF
0xF_FF1F_FFFF
0x0_1FFF_FFFF
0xF_FF1F_0000
0x0_1FC0_0000
Figure 4.1.1 Physical Address Map at Initializing System
0x0_0000_0000
36
) bytes of physical address.
External Bus Controller Channel 0
TX4937 Internal Register
4-1
Chapter 4 Address Mapping
64 K Bytes
4 M Bytes