TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 108

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Upper Address
Lower Address
7.3.5.3
ADDR Bit
8-bit Bus Width Mode
which are the upper address, are multiplexed to external ADDR[19:12]. In other words, the
address is shifted up two bits or more relative to the 32-bit bus mode when output. As a result, the
maximum memory size of the 8-bit bus mode is 256 MB.
the external bus. 8-bit access is executed twice when performing 1-half-word access. 8-bit access
is executed four times when performing 1-word access. 8-bit access is executed eight times when
performing 1-double-word access. When a Burst cycle is executed, eight 8-bit cycles are executed
for each Burst access when the Bus cycle tries to request a byte combination other than double-
word data.
Table 7.3.6 Address Output Bit Correspondence in the 8-bit Mode
DATA[7:0] becomes valid.
Bits [19:0] of the physical address are output to ADDR[19:0]. The internal address bits [27:20],
When a Single cycle that accesses 1-Byte data is executed, 8-bit access is executed only once on
19 18 17 16 15 14 13 12 11 10 9
27 26 25 24 23 22 21 20
19 18 17 16 15 14 13 12 11 10
7-8
Chapter 7 External Bus Controller
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0