TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 545

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

TMPR4937 Revision History
Page
3-11
1-1
3-7
3-7
3-7
3-8
4-1
5-2
References
64-bit TX System RISC TX49/H3 Core Architecture User’s
Manual
Modified line 5 of the body text in Section 1.1, Overview
For details of the TX49/H3 core such as instruction sets, see
“64-bit TX System RISC TX49/H3 Core Architecture”.
Table 3.1.11 Extended EJTAG Interface Signals
Changed the description of the TRST* signal
When an EJTAG probe is not connected, this pin must be
fixed to low. When connecting an EJTAG probe, prevent
floating, for example, by connecting a pull-up resistor.
Table 3.2.2 Boot Configuration Specified with the
ADDR[19:0] Signals (1/2)
Modified the description of the ADDR[17:15].
Reserved
Modified line 2 of the introduction in Chapter 4, Address
Mapping
Please refer to "64 bit TX System RISC TX49/H3 Core
Architecture" about the details of mapping to a physical
address from the virtual address of TX49/H3 core.
Table 5.2.1 Configuration Register Mapping
Deleted the description of the Jump Address Register
Rev 1.1 Manual
1
64-bit TX System RISC
Architecture
For details of the TX49/H3 core such as instruction sets,
see “64-bit TX System RISC
Core Architecture”.
Table 3.1.9 AC-link Interface Signals
Added the following text to the description of the SDIN[1]
signal
When this pin is used as SDIN[1], pull down by the resister
on the board. (Regarding the value of register, please ask
the Engineering Department in Toshiba).
Table 3.1.9 AC-link Interface Signals
Added the following text to the description of the SDIN[0]
signal
When this pin is used as SDIN[0], pull down by the resister
on the board. (Regarding the value of register, please ask
the Engineering Department in Toshiba).
Table 3.1.9 AC-link Interface Signals
Added the following text to the description of the BITCLK
signal
When this pin is used as BITCLK, pull down by the resister
on the board. (Regarding the value of register, please ask
the Engineering Department in Toshiba).
TRST* pin must be pulled down (ex.10 kΩ).
Reserved
Used for testing. This signal will not be set to 0 upon
booting.
Please refer to
TX49/H4
a physical address from the virtual address of TX49/H3
core.
Deleted
TMPR4937 Revision History
Changes and Additions to Rev 1.1
Core Architecture" about the details of mapping to
"64-bit
TX System RISC
TX49/H2, TX49/H3, TX49/H4 Core
TX49/H2, TX49/H3, TX49/H4
TX49/H2, TX49/H3,