TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 176

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

8.3.11
7.
8.
Dynamic Chain Operation
while Chain DMA transfer is in progress. This is performed according to the following procedure.
1.
2.
3.
It is possible to add DMA Command Descriptor chains to the DMA Command Descriptor chain
Initiate DMA transfer
Setting the address of the DMA Command Descriptor at the beginning of the chain list in the DMA
Chain Address Register (DMCHARn) automatically initiates DMA transfer. First, the value stored
in each field of the DMA Command descriptor at the beginning of the Chain List is read to each
corresponding DMA Channel register (Chain transfer), then DMA transfer is performed according
to the read value.
When a value other than “0” is stored in the DMA Chain Address Register (DMCHARn), data of
the size stored in the DMA Count Register (DMCNTRn) is completely transferred, then the DMA
Command Descriptor value of the memory address specified by the DMA Chain Address Register
is read.
In addition, if the Chain Address field value read the Descriptor 0, the DMA Chain Address
Register value is not updated. All previous values (Data Command Descriptor Addresses with the
value “0” in the Chain Address field when the values were read) are held.
0 Value judgement is performed when the lower 32 bits of the DMA Chain Address Register are
rewritten. If the value is not “0” at this time, DMA transfer is automatically initiated. Therefore,
please write to the upper 32 bits first when writing to the DMA Chain Address Register using 32-
bit Store instructions.
Signal completion
Set the Normal Chain End bit (NCHNC) of the DMA Channel Status Register (DMCSRn) when
DMA data transfer of all Descriptor Chains is complete. An interrupt is signalled if the Chain End
Interrupt Enable bit (INTENC) of the DMA Channel Control Register (DMCCRn) is set at this
time.
In addition, the Normal Transfer End bit (NTRNFC) of the DMA Channel Status Register
(DMCSRn) is set each time DMA data transfer specified by each DMA Command Descriptor ends
normally. An interrupt is signalled if the Transfer End Interrupt Enable bit (INTENT) of the DMA
Channel Control Register (DMCCRn) is set at this time.
If an error is detected during DMA transfer, the error cause is recorded in the lower four bits of the
DMA Channel Status register and transfer is interrupted. An interrupt is signalled if the Error
Interrupt Enable bit (INTENE) of the DMA Channel Control Register is set.
Construct the DMA Command Descriptor chain
Construct the DMA Command Descriptor chain to be added to memory.
Add a DMA Command Descriptor chain
Substitute the address of the Command Descriptor at the beginning of the Descriptor Chain to be
added into the Chain Address field of the Descriptor at the end of the DMA Command Descriptor
chain that is currently performing DMA transfer.
Check the Chain Enable bit
Read the value of the Chain Enable bit (CHNEN) of the DMA Channel Control Register
(DMCCRn). If that value is “0”, then write the Chain Address field value of the DMA Command
Descriptor that is indicated by the address stored in the DMA Chain Address Register
(DMCHARn).
8-20
Chapter 8 DMA Controller