TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 260

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

10.1.3
10.1.4
10.1.5
Target Function
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PCI Arbiter
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PDMAC (PCI DMA Controller)
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Single and Burst transfer from the PCI Bus to the Internal Bus
Supports memory, I/O, and configuration cycles
Supports high-speed back-to-back transactions on the PCI Bus
Address mapping between the PCI Bus and the Internal bus can be modified
Mounted 8-stage 64-bit data FIFO for Read
Mounted 12-stage 64-bit data FIFO for Write
Post Write function enables quick termination of a maximum of nine Write transactions by the PCI
Bus without waiting for completion on the G-Bus.
Read Burst length (pre-fetch data size) on the Internal Bus when reading a pre-fetchable space can
be made programmable
Endian switching function
Supports four external PCI bus masters
Uses the Programmable Fairness algorithm (two levels with different priorities for four round-
robin request/grant pairs)
Supports bus parking
Bus master uses the Most Recently Used algorithm
Unused slots and broken masters can be automatically disabled after Power On reset
On-chip arbitration function can be disabled and external arbiter can be used
Direct Memory Access (DMA) Controller dedicated to 1-channel PCI
Is possible to transfer data using minimal G-Bus bandwidth
Data can be transferred bidirectionally between the G-Bus and the PCI Bus
Specifying a physical address on the PCI Bus and an address on the G-Bus makes it possible to
automatically transfer data between the PCI Bus and the G-Bus
Supports the Chain DMA mode, in which a Descriptor containing chain-shaped addresses and a
transfer size is automatically read from memory while DMA transfer continuous
On-chip 4-stage 64-bit data buffer
10-2
Chapter 10 PCI Controller