TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 423

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

31:24
Bit
23
22
21
20
19
18
14.4.1
MODID
R/W1S R/W1S
MA
31
15
0
Mnemonic
MODOEHLT Enable Modem
CENTEHLT
AUDIEHLT
LFEEHLT
MODO
⎯
⎯
DMA
30
14
0
ACLC Control Enable Register
This register is used to check the setting of various ACLC features and to enable them.
Reserved
29
13
Reserved
Enable Modem
Receive-data
DMA Error Halt
Transmit-data
DMA Error Halt
Reserved
Enable Audio
Receive-data
DMA Error Halt
Enable Audio
LFE
Transmit-data
DMA Error Halt
Enable Audio
Center
Transmit-data
DMA Error Halt
Field Name
AUDID
R/W1S R/W1S R/W1S R/W1S R/W1S
MA
28
12
Reserved
0
LFEDM
27
11
A
0
MODIEHLT: Enable Modem Receive-data DMA Error Halt.
MODOEHLT: Enable Modem Transmit-data DMA Error Halt.
AUDIEHLT: Enable Audio Receive-data DMA Error Halt.
LFEEHLT: Enable Audio LFE Transmit-data DMA Error Halt.
CENTEHLT: Enable Audio Center Transmit-data DMA Error Halt.
Figure 14.4.1 ACCTLEN Register (1/3)
W1S
W1S
W1S
W1S
W1S
CENTD
R
R
R
R
R
MA
26
10
0
0: Indicates that MODIDMA error halt is disabled.
1: Indicates that MODIDMA error halt is enabled.
0: No effect
1: Enables MODIDMA error halt. When MODIDMA overrun
0: Indicates that MODODMA error halt is disabled.
1: Indicates that MODODMA error halt is enabled.
0: No effect
1: Enables MODODMA error halt. When MODODMA underrun
0: Indicates that AUDIDMA error halt is disabled.
1: Indicates that AUDIDMA error halt is enabled.
0: No effect
1: Enables AUDIDMA error halt. When AUDIDMA overrun occurs,
0: Indicates that LFEDMA error halt is disabled.
1: Indicates that LFEDMA error halt is enabled.
0: No effect
1: Enables LFEDMA error halt. When LFEDMA underrun occurs,
0: Indicates that CENTDMA error halt is disabled.
1: Indicates that CENTDMA error halt is enabled.
0: No effect
1: Enables CENTDMA error halt. When CENTDMA underrun
SURR
DMA
occurs, subsequent DMA will not be issued.
occurs, subsequent DMA will not be issued.
subsequent DMA request will not be issued.
subsequent DMA request will not be issued.
occurs, subsequent DMA request will not be issued.
25
9
0
AUDO
DMA
24
8
0
14-17
MODIE
R/W1S R/W1S
HLT
23
0
7
Reserved
Description
MODOE
HLT
22
0
6
Chapter 14 AC-link Controller
Reserved
0xF700
RDYCLR MICSEL WRESET WAKEUP
W1S
21
5
0
AUDIE
R/W1S R/W1S R/W1S R/W1S R/W1S
R/W1S R/W1S R/W1S R/W1S R/W1S
HLT
20
4
0
0
LFEEH
19
LT
3
0
0
CENTE
HLT
18
2
0
0
SURRE
LOW
PWR
HLT
17
1
0
0
Read/Write
R/W1S
R/W1S
R/W1S
R/W1S
R/W1S
ENLINK
AUDO
EHLT
16
0
0
0
⎯
⎯
: Type
: Initial value
: Type
: Initial value