TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 550

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Page
11-22
12-10
14-11
15-5
20-2
20-3
20-3
20-7
Figure 11.4.7 Baud Rate Control Register
Modified the description of the BCLK (Baud Rate Generator
Clock) field.
00: Select prescalar output T0 (IMBUSCLK/2)
01: Select prescalar output T2 (IMBUSCLK/8)
10: Select prescalar output T4 (IMBUSCLK/32)
11: Select prescalar output T6 (IMBUSCLK/128)
Table 14.3.7 Mic DMA Buffer Format in Big-endian Mode
Modified line 3 of Section 15.3.1, Interrupt sources
Please refer to the 64-bit TX System RISC TX49/H3 Core
Architecture Manual for more information.
Modified line 2 of Section 20.2.1, JTAG Controller and
Register
Please refer to the TX49/H3 Core Architecture Manual for
all other portion not covered here.
Modified line 3 of 20.2.2, Instruction Register
Refer to the TX49/H3 Core Architecture Manual for more
information regarding each instruction.
Table 20.2.1 Bit Configuration of JTAG Instruction Register
Refer to the TX49/H3 Core Architecture Manual
Modified line 5 of Section 20.3, Initializing the Extended
EJTAG Interface
(Hold the signal low for 2 or more clock cycles of the TCK
input.)
After that, deassert the TRST* signal High.
Address offset
+4
+8
z
:
Rev 1.1 Manual
#0
#1
#2
+0
:
H
H
H
#0
#1
#2
+1
:
L
L
L
6
00: Select prescalar output T0 (fc/2)
01: Select prescalar output T2 (fc/8)
10: Select prescalar output T4 (fc/32)
11: Select prescalar output T6 (fc/128)
Figure 12.4.1 Timer Control Register
Added the following text to the description of the Counter
Reset Enable field
During CRE = 1, reset the counter if TCE is set from 1 to 0.
During TCE = 0, the counter isn’t reset if CRE is set from 0
to 1.
When TCE = 1 and CRE = 0, stop and reset the counter if
TCE is set to 0 and CRE is set to 1 simultaneously.
Please refer to the
TX49/H3, TX49/H4 Core Architecture”
Please refer to the
TX49/H3, TX49/H4 Core Architecture”
not covered here.
Refer to the
TX49/H4 Core Architecture”
each instruction.
Refer to the
TX49/H4 Core Architecture”
(TRST * signal is pulled down (by ex. 10 k Ω ))
Address offset
TMPR4937 Revision History
Changes and Additions to Rev 1.1
“64-bit TX System RISC TX49/H2, TX49/H3,
“64-bit TX System RISC TX49/H2, TX49/H3,
+0
+4
+8
:
“64-bit TX System RISC TX49/H2,
“64-bit TX System RISC TX49/H2,
for more information regarding
#0
#1
#2
+0
:
H
H
H
for more information.
for all other portion
#0
#1
#2
+1
:
L
L
L