TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 174

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

8.3.10
Offset Address
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
Chain DMA Transfer
Simple Chain bit (SMPCHN) of the DMA Channel Control Register (DMCCRn) is set, only the initial
four double words are used. DMSAIRn, DMDAIR, DMCCRn, and DMCSRn use the settings from
when DMA started. In addition, all eight double words are used when the Simple Chain bit (SMPCHN)
is cleared.
Address field makes it possible to construct a chain list of DMA Command Descriptors (Figure 8.3.5).
Set “0” in the Chain Address field of the DMA Command Descriptor at the end of the chain list.
automatically reads the next DMA Command Descriptor indicated by the Chain Address Register
(Chain transfer), then continues DMA transfer. Continuous DMA transfer that uses multiple Descriptors
connected into such a chain-like structure is called Chain DMA transfer.
Simple Chain bit (SMPCHN) is cleared, be sure not to unnecessarily clear necessary bits.
in memory is efficient since they are read by one G-Bus Burst Read operation.
Table 8.3.4 shows the data structure in memory that the DMA Command Descriptor has. When the
Saving the start memory address of another DMA Command Descriptor in the Offset 0 Chain
When DMA transfer that is specified by one DMA Command Descriptor ends, the DMA Controller
Since the DMA Channel Status Register is also overwritten during Chain transfer when the DMA
Placing DMA Command Descriptors at addresses that do not span across 32-double-word boundaries
Chain Address
Source Address
Destination Address
Count
Source Address Increment
Destination Address Increment
Channel Control
Channel Status
Field Name
Table 8.3.4 DMA Command Descriptors
8-18
DMA Chain Address Register (DMCHARn)
DMA Source Address Register (DMSARn)
DMA Destination Address Register (DMDARn)
DMA Count Register (DMCNTRn)
DMA Source Address Increment Register (DMSAIRn)
DMA Destination Address Increment Register (DMDAIRn)
DMA Channel Control Register (DMCCRn)
DMA Channel Status Register (DMCSRn)
Transfer Destination Register
Chapter 8 DMA Controller