TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 67

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

DATA[22:16]
DATA[15:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1:0]
Signal
Reserved
Boot Configuration
Reads the board information and accordingly sets the boot
configuration field (BCFG) of the chip configuration register (CCFG).
TX49/H3 Internal Timer Interrupt Disable
Specifies whether timer interrupts within the TX49/H2 core are
enabled.
H = Enable timer interrupts within the TX49/H3 core.
L = Disable timer interrupts within the TX49/H3 core.
Reserved
Specifies the function of the BE[3:0]*/BWE[3:0]* pins upon booting.
L = BE[3:0]* (Byte Enable)
H = BWE[3:0]* (Byte Write Enable)
Boot ACK* Input
Specifies the access mode for external bus controller channel 0.
L = External ACK mode
H = Normal mode
Reserved
PCI Arbiter Select
Selects a PCI bus arbiter.
L = External PCI bus arbiter.
H = Built-in PCI bus arbiter.
Boot ROM Bus Width
Specifies the data bus width when booting from a memory device
connected to the external bus controller.
LL = Reserved
LH = 32 bits
HL = 16 bits
HH = 8 bits
Table 3.2.3 Boot Configuration Specified with the DATA[22:0] Signals
Description
3-13
CCFG.BCFG
CCFG.TINTDIS
EBCCR0.BC
EBCCR0.WT[0]
CCFG.PCIARB
EBCCR0.BSZ
Corresponding
Register Bit
Chapter 3 Signals
⎯
⎯
⎯
RESET* deassert edge
RESET* deassert edge
RESET* deassert edge
RESET* deassert edge
RESET* deassert edge
RESET* deassert edge
Determined at
Configuration
⎯
⎯
⎯