TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 332

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

31:11
Bit
10
31
15
9
8
7
6
5
4
3
10.4.44 PCI Controller Status Register (PCICSTATUS)
Mnemonic
PERR
SERR
PME
GBE
TLB
NIB
ZIB
Reserved
Reserved
PME Detect
Long Burst
Transfer Detect
Negative
Increment Burst
Detect
Zero Increment
Burst Detect
Reserved
PERR* Detected
SERR* Detected
G-Bus Error
Detect
Field Name
11
Figure 10.4.42 PCI Controller Status Register (1/2)
R/W1C R/W1C R/W1C R/W1C
PME
0x0
10
PME Detect (Default: 0x0)
When the PCI Controller is in the Host mode, this bit indicates that
assertion of the PME* signal was detected.
1: Indicates that assertion of the PME* signal was detected.
0: Indicates that assertion of the PME* signal was not detected.
Too Long Burst Detect (Default: 0x0)
Indicates that a Burst transfer by the on-chip DMA Controller exceeding 8
DWORDs was detected.
1: Indicates that a Burst transfer exceeding 8 DWORDs was detected.
0: Indicates that no Burst transfer exceeding 8 DWORDs was detected.
Negative Increment Burst Detect (Default: 0x0)
Indicates that Burst transfer by the on-chip DMA Controller in the negative
direction was detected.
1: Indicates that a Burst transfer in the negative direction was detected.
0: Indicates that no Burst transfer in the negative direction was detected.
Zero Increment Burst Detect (Default: 0x0)
Indicates that Burst transfer by the on-chip DMA Controller without an
address increment was detected.
1: Indicates that a Burst transfer without an address increment was
0: Indicates that no Burst transfer without an address increment was
PERR* Occurred (Default: 0x0)
Indicates that the Parity Error signal (PERR*) was asserted. This bit is a
monitor status bit that records assertion of the PERR* signal even if the
TX4937 is not accessing PCI.
1: Indicates that the PERR* signal was asserted.
0: Indicates that the PERR* signal was not asserted.
SERR* Occurred (Default: 0x0)
Indicates that the System Error signal (SERR*) was asserted. This bit is a
monitor status bit that records assertion of the SERR* signal even if the
TX4937 is not accessing PCI.
1: Indicates that the SERR* signal was asserted.
0: Indicates that the SERR* signal was not asserted.
G-Bus Error Detect (Default: 0x0)
Indicates that a G-Bus Error occurred in the G-Bus Master cycle of the PCI
Controller. This error is indicated when a timeout occurs on the G-Bus. This
bit is only set by Master cycle Bus Errors.
1: Indicates that a G-Bus Error was detected.
0: Indicates that no G-Bus Error was detected.
detected.
detected.
TLB
0x0
9
NIB
0x0
Reserved
8
10-74
ZIB
0x0
7
Reserved
Description
6
R/W1C R/W1C R/W1C
PERR SERR
0x0
5
Chapter 10 PCI Controller
0xD174
0x0
4
GBE
0x0
3
Reserved
2
IWB
0x0
R
1
E2PDONE
Read/Write
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
16
⎯
R
0
⎯
⎯
: Type
: Initial value
: Type
: Initial value