TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 219

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

9.3
9.3.1
Note1: The SDRAM Controller logic-wise does support these configurations, but please design carefully since the memory
Note2: This SDRAM configuration has 512 Mbytes of memory on a channel. If it is mapped to physical address space
128 Mbit
256 Mbit
512 Mbit
16 Mbit
64 Mbit
Detailed Explanation
SDRAM Configuration
bus load will be large.
beginning with address 0, it overlaps the address space for the ROM wherein the bootstrap vectors reside.
Supported SDRAM configurations
data bus width for each channel to either 64 bits or 32 bits.
DATA[63:32] output an undefined value when DATA[31:0] become the output, but enter the High-Z
state when DATA[31:0] are the input. When in the Big Endian Mode, first external access of the upper
word (bits 63:32) of the internal data bus is performed, then external access of the lower word (bits
31:0) is performed. When in the Little Endian Mode, first external access of the lower word (bits 31:0)
is performed, then external access of the upper word (bits 63:32) is performed. When using a 32-bit data
bus, two external access will always be performed even when accessing less than 32 bits of data.
using 16 512-Mbit SDRAMs with a 4-bit data bus. The total maximum memory capacity is 4 GBytes
when totaling up the four channels.
This controller supports the SDRAM configurations listed below in Table 9.3.1.
The MW field of the SDRAM Channel Control Register (SDCCRn) can be used to separately set the
DATA[31:0] and DQM[3:0] are used when using a 32-bit data bus. DQM[7:4] output High.
The maximum memory capacity per channel when a 64-bit data bus is configured is 1 GBytes when
2-bank
2-bank
4-bank
4-bank
4-bank
4-bank
16 M × 16
32 M × 16
128 M × 4
1 M × 16
2 M × 32
2 M × 32
4 M × 16
4 M × 16
16 M × 4
2 M × 32
4 M × 16
16 M × 4
4 M × 32
8 M × 16
16 M × 8
32 M × 4
32 M × 8
64 M × 4
64 M × 8
2 M × 8
4 M × 4
8 M × 8
8 M × 8
Table 9.3.1 Supported SDRAM Configurations
Row Address (bit)
11
11
11
11
12
11
13
13
13
11
12
12
12
12
12
12
12
13
13
13
13
13
13
9-3
Column Address (bit)
Chapter 9 SDRAM Controller
10
10
10
10
10
11
10
11
10
11
12
8
9
9
8
8
9
8
8
9
8
9
9
See Note 1,2
See Note 1,2
See Note 1
See Note 1
See Note 1
See Note 1
See Note 2
Remarks