TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 88

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

48:45
44:41
39:33
31:30
29:28
26:23 SDCLKEN [3:0] SDCLK Enable Individually specifies whether to output each of SDCLK[3:0].
21:16 PCICLKEN [5:0] PCICLK Enable Individually specifies whether to output each of PCICLK[5:0].
15:10
Bit
49
40
32
27
22
9
BYPASS PLL Bypass PLL
Mnemonic
SDCLKINEN
DRVCS[3:0]
DRVCK[3:0]
SDCLKDLY
SYSCLKEN
DRVCKIN
DRVWE
SEL2
⎯
⎯
⎯
WE Signal
Control
SDRAM CS
Signal Control
SDRAM SDCLK
Signal Control
SDRAM
SDCLKIN
Signal Control
Reserved
Reserved
SDCLK
Feedback Delay
SYSCLK Enable Specifies whether to output the SYSCLK.
SDCLKIN
Enable
Reserved
Shared-Pin
Status 2
Field Name
Figure 5.2.3 Pin Configuration Register (2/3)
Specifies the driving capability of the WE* signal.
L : 0 = 8 mA
H : 1 = 16 mA
Specifies the driving capability of the SDCS[3:0]* signals.
L : 0 = 8 mA
H : 1 = 16 mA
Specifies the driving capability of the SDCLK[3:0] signals.
L : 0 = 8 mA
H : 1 = 16 mA
Specifies the driving capability of the SDCLKIN signal.
L : 0 = 8 mA
H : 1 = 16 mA
Indicates information about whether a PLL for a circuit other
than the PCI controller is on or off.
L: 0 = The PLL is off.
H: 1 = The PLL is on.
Specifies the feedback delay for the SDCLK. This function is
for diagnosis purposes. Usually, set the bits to 00.
00 = Delay 1 (minimum delay)
10 = Delay 2
01 = Delay 3
11 = Delay 4 (maximum delay)
1 = Clock output
0 = H
1 = Clock output
0 = H
Bit 26 = SDCLK[3]
Bit 25 = SDCLK[2]
Bit 24 = SDCLK[1]
Bit 23 = SDCLK[0]
Specifies how SDCLK[3:0] should be fed back. This function
is for diagnosis purposes. Usually, set this bit to 0.
0 = Use the SDCLKIN signal as a feedback clock.
1 = Perform feedback within the TX4937 (the SDCLKIN
1 = Clock output
0 = H
Bit 21 = PCICLK[5]
Bit 20 = PCICLK[4]
Bit 19 = PCICLK[3]
Bit 18 = PCICLK[2]
Bit 17 = PCICLK[1]
Bit 16 = PCICLK[0]
DMAREQ[2], DMAACK[2], and PIO[4:2] share pins with the
AC-link interface signals. Indicates which function the shared
pins are set to.
L: 0 = The shared pins are set to DMAREQ[2], DMAACK[2],
H: 1 = The shared pins are set to the AC-link interface signals.
becomes an output signal).
and PIO[4:2].
5-8
Description
⎯
⎯
⎯
Chapter 5 Configuration Registers
BYPASSPLL* R
Initial Value Read/Write
ADDR[5]
ADDR[5]
ADDR[5]
ADDR[5]
00
1
1111
0
111111
ADDR[9]
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
⎯
⎯
⎯