TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 165

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

8.3.5
8.3.6
8.3.7
Memory-Memory Copy Mode
Memory-Memory Copy mode.
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ownership of each bus using the Internal Request Delay field (INTRQD) of the DMA Channel Control
Register (DMCCRn).
Memory Fill Transfer Mode
Register (DMMFDR) is written to the data region specified by the DMA Source Address Register
(DMSARn). This data can be used for initializing the memory, etc.
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•
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ownership of each bus using the Internal Request Delay field (INTRQD) of the DMA Channel Control
Register (DMCCRn).
Controller memory channels simultaneously (refer to Section 9.3.4), it is possible to initialize memory
even more efficiently.
Single Address Transfer
applies to the following DMA Transfer modes.
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It is possible to copy memory from any particular address to any other particular address when in the
Set the DMA Channel Control Register (DMCCRn) as follows.
Furthermore, when in the Memory-Memory Copy mode it is possible to set the interval for requesting
Refer to “8.3.8 Dual Address Transfer” for information regarding the setting of other registers.
When in the Memory Fill Transfer mode, double word data set in the DMA Memory Fill Data
Set the DMA Channel Control Register (DMCCRn) as follows.
In addition, when in the Memory Fill Transfer mode, it is possible to set the interval for requesting
Refer to “8.3.7 Single Address Transfer” for information regarding the setting of other registers.
By using this function together with the memory Write function that writes to multiple SDRAM
This section explains register settings during Single Address transfer (DMCCRn.SNGAD = 1). This
DMCCRn.EXTRQ = 0: Memory Transfer mode
DMCCRn.SNGAD = 0: Dual Address mode
DMCCRn.EXTRQ = 0: Memory transfer mode
DMCCRn.SNGAD = 1: Single Address Transfer
DMCCRn.MEMIO = 0: Transfer from I/O to memory
External I/O (Single Address) Transfer
Memory Fill Transfer
8-9
Chapter 8 DMA Controller