TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 388

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

12.3.3
12.3.4
Divide
Rate
128
256
16
32
64
2
4
8
Counter
the 32-bit counter will start counting.
(TMTCRn.CRE) is set, then the counter will be cleared also. The Watchdog Timer Disable bit
(TMWTRM2.WDIS) must be set in order to stop and clear this counter when in the Watch Dog Timer
mode.
Interval Timer Mode
(TMTCRn.TMODE) of the Timer Control Register to “00” sets the timer to the Interval Timer mode.
This mode can be used by all timers.
TMCPRA Status bit (TMTISRn.TIIS) of the Timer Interrupt Status Register is set. When the Interval
Timer Interrupt Enable bit (TMITMRn.TIIE) of the Interval Timer Mode Register is set, timer interrupts
occur. When a “0” is written to the Interval Timer TMCPRA Status bit (TMTISRn.TIIS), TIIS is cleared
and timer interrupts stop.
value matches the Compare Register A (TMCPRAn) value. Count operation stops when the Timer Zero
Clear Enable bit (TMITMRn.TZCE) is cleared.
undefined when changing from the Pulse Generator mode to this mode. Figure 12.3.1 shows an outline
of the count operation and generation of interrupts when in the Interval Timer mode and Figure 12.3.2
shows the operation when using an external input clock.
Each channel has an independent 32-bit counter. Set the Timer Count Enable bit (TMTCRn.TCE) and
Clear the Timer Count Enable bit to stop the counter. If the Counter Reset Enable bit
Also, reading the Timer Read Register (TMTRR) makes it possible to fetch the counter value.
The Interval Timer mode is used to periodically generate interrupts. Setting the Timer Mode field
When the count value matches the value of Compare Register A (TMCPRAn), the Interval Timer
If the Timer Zero Clear Enable bit (TMITMRn.TZCE) is set, the counter is cleared to 0 if the count
The level of the TIMER[1:0] output signal stays in the initial state (Low) in this mode. Output is
TMCCDRn.
CCD
000
001
010
011
100
101
110
111
Table 12.3.2 Divide Value and Count (IMBUSCLK = 66 MHz)
Frequency (Hz)
Counter Clock
1031.3 K
515.6 K
257.8 K
33.0 M
16.5 M
8.3 M
4.1 M
2.1 M
Resolution (ns)
12-4
1939.39
3878.79
121.21
242.42
484.85
969.70
30.30
60.61
Max. Set Time
Chapter 12 Timer/Counter
(sec.)
16659.27
1041.20
2082.41
4164.82
8329.63
130.15
260.30
520.60
TMCPRAn Value
for 1 sec.
33000000
16500000
8250000
4125000
2062500
1031250
515625
257813