TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 289

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

BISTC
30:24
22:16
15:8
Bit
7:0
31
23
31
15
R
0
10.4.4
Mnemonic
30
MFUNS
BISTC
CLS
HT
LT
PCI Configuration 1 Register (PCICFG1)
The following fields correspond to the following registers.
This register cannot be accessed when the PCI Controller is in the Satellite mode.
BIST field → BIST Register of the PCI Configuration Space
Header Type field → Header Type Register in the PCI Configuration Space
Latency Timer field → Latency Timer Register of the PCI Configuration Space
Cache Line Size field → Cache Line Size Register of the PCI Configuration Space.
BIST Capable
Reserved
Multi-Function
Header Type
Latency Timer
Cache Line Size
Field Name
0x00
R/W
LT
Reserved
Figure 10.4.4 PCI Configuration 1 Register
BIST Capable (Fixed Value: 0)
Indicates that the BIST function is not being supported.
Multi-Function (Fixed Value: 0)
0: Indicates that the device is a single-function device.
Header Type (Default: 0x00)
Indicates the Header type.
0000000: Header Type 0
It is possible to change the header type by loading data from Configuration
EEPROM during initialization.
Latency Timer (Default: 0x00)
Sets the latency timer value. Specifies the PCI Bus clock count during
which to abort access when the GNT* signal is deasserted during PCI
access. Since the lower two bits are fixed to “0”, cycle counts can only be
specified in multiples of 4.
Cache Line Size (Default: 0x00)
Is used to select the PCI Bus command during a Burst Read transaction.
See “10.3.3 Supported PCI Bus Commands)” for more information.
24
8
10-31
MFUNS
23
R
0
7
22
Description
0xD00C
Chapter 10 PCI Controller
0x00
CLS
R/W
0x00
R/L
HT
Read/Write
R
R
R/L
R/W
R/W
16
0
⎯
: Type
: Initial value
: Type
: Initial value