TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 66

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

ADDR[4]
ADDR[3:0]
Signal
Initial Setting of Boot
Select initial setting derivability of SDRAM interface signals
L = 8mA
H = 16mA
DATA[63:0], CB[7:0], DQM[7:0]
CPUCLK Clock Speed Setting
Specifies the value by which MASTERCLK input signal is multiplied
to produce the TX49/H3 core clock (CPUCLK).
The values of ADDR[1:0] are also reflected in the EC field of the
TX49/H3 core Config register.
ADDR[3:0] : DIVMODE[3:0]
HHHH:0100 CPUCLK frequency = 2 x MASTERCLK frequency
HHHL:1111 CPUCLK frequency = 2.5 x MASTERCLK frequency
HHLH:0101 CPUCLK frequency = 3 x MASTERCLK frequency
HHLL:0110 CPUCLK frequency = 4 x MASTERCLK frequency
LHHH:1101 CPUCLK frequency = 4.5 x MASTERCLK frequency
LHHL: -
LHLH: -
LHLL: -
HLHH:0000 CPUCLK frequency = 8 x MASTERCLK frequency
HLHL:1011 CPUCLK frequency = 10 x MASTERCLK frequency
HLLH:0001 CPUCLK frequency = 12 x MASTERCLK frequency
HLLL:0010 CPUCLK frequency = 16 x MASTERCLK frequency
LLHH:1001 CPUCLK frequency = 18 x MASTERCLK frequency
LLHL: -
LLLH: -
LLLL: -
Table 3.2.2 Boot Configuration Specified with the ADDR[19:0] Signals (2/2)
reserved
reserved
reserved
reserved
reserved
reserved
Description
3-12
CCFG.DIVMODE
PCFG[56:54]
Corresponding
Register Bit
Chapter 3 Signals
RESET* deassert edge
CGRESET* deassert
edge
Determined at
Configuration