TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 237

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

1
2
22:18
13:12
11:0
t
t
Bit
24
23
17
16
15
14
CK
RC
t
RP
is used during (i) refresh cycle time, (ii) single Read, (iii) two transfer burst Reads. The bank cycle time is t
= Clock cycle
+ 1t
Mnemonic
CK
PDAE
CASL
SWB
DRB
ACE
if t
RC
DA
RP
—
RAS
+ t
RP
Advanced CKE
Power Down
Auto Entry
Refresh Counter
CAS Latency
Data Read
Bypass
Active Command
Delay
Slow Write Burst
Refresh Period
Field Name
< t
RC
—
in the case of (ii) (iii).
Figure 9.4.2 SDRAM Timing Register (2/2)
Advanced CKE enable (Default: 0)
Enabling this function makes the timing at which CKE changes one cycle
earlier.
0: Disable
1: Enable
Power Down Auto Entry Enable (Default: 0)
Enabling this function makes CKE become “L” while the SDRAMC is in the
Idle state. When refresh, memory access, or command execution is
performed, CKE automatically becomes “H”, the requested operation is
performed, then CKE returns to “L” when the operation is complete.
0: Disable
1: Enable
Refresh Counter (Default: 000000)
This counter is decremented at each refresh. If the refresh circuit is
activated and a value other than “0” is loaded, this field becomes a down
counter that stops at “0”. A value other than “0” must be reloaded to start
the countdown again. This is used during memory initialization.
CAS Latency (t
Specifies the CAS latency.
0: 2 t
1: 3 t
Data Read Bypass (Default: 0)
Selects the Data Read path used.
0: Data Read latches to the register using the feedback clock.
1: Data Read bypasses the feedback clock latch.
Delay Activate (t
Specifies the delay from the row address to the bank active command.
Setting this bit to “1” sets up the row address two cycles before the active
command is executed.
0: 0 t
1: 1 t
Slow Write Burst (t
Specifies whether to perform Slow Write Burst.
0: Burst Write occurs at each 1 t
1: Burst Write occurs at each 2 t
Reserved
Refresh Period (Default: 0x30c)
Specifies the clock cycle count that generates the refresh cycle. Refresh is
only enabled when at least one SDRAM channel is enabled. Please
program the Timing Register before an arbitrary channel is enabled.
Default is 0x30C. A refresh cycle occurs for each 7.8 µs@100 MHz in this
situation.
CK
CK
CK
CK
CASL
DA
SWB
) (Default: 1)
9-21
) (Default: 1)
) (Default: 1)
Description
CK
CK
Chapter 9 SDRAM Controller
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAS
⎯
+