TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 162

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

OE*/BUSSPRT*
ADDR [19:0]
DMADONE*
DMAREQ[n]
DMAACK[n]
DATA [31:0]
SYSCLK
SWE*
BWE*
ACE*
ACK*
CE*
Figure 8.3.1 External I/O DMA Transfer (Single Address, Level Request)
•
diagram, both the DMAREQ[n] signal and the DMAACK[n] signal are set to Low active
(DMCCRn.REQPL = 0, DMCCRn.ACKPOL = 0).
synchronized to SDCLK. When these signals are used by an external I/O device that is
synchronous to SYSCLK, it is necessary to take clock skew into account.
the CE*/CS* signal, or before that. In addition, it is deasserted after the last ACK*/READY signal
is deasserted.
least one SYSCLK cycle while the DMAACK[n] signal is asserted either during the same
SYSCLK cycle that the CE*/CS* signal is deasserted or during a subsequent SYSCLK cycle.
When the DMADONE* signal is used as an input signal, it must be asserted for one SYSCLK
cycle while the DMAACK[n] signal is being asserted.
Figure 8.3.1 is a timing diagram that shows the timing of external DMA access. In this timing
The DMAACK[n] and DMADONE[n] signals, which are DMA control signals, are
The DMAACK[n] signal is asserted either at the SYSCLK cycle, the same as with assertion of
When the DMADONE* signal (refer to 8.3.3.4) is used as an output signal, it is asserted for at
1 cycle
When edge detection is set (DMCCRn.EGREQ = 1)
after the DMAACK[n] signal corresponding to a previously asserted DMAREQ[n] signal is
deasserted. The DMAREQ[n] signal will not be detected even if it is asserted before
DMAACK[n] is deasserted.
Please set up assertion of the DMAREQ[n] signal so the DMAREQ[n] signal is asserted
1c040
8-6
f
00000100
00040
Chapter 8 DMA Controller