TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 87

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

63:57
63
47
31
15
Reserved
Bit
56
55
54
53
52
51
50
DRVCS[2:0]
5.2.3
ADDR[5]
R/W
30
Mnemonic
DRVADDR
DRVDATA
DRVDQM
DRVCKE
DRVRAS
DRVCAS
DRVCB
⎯
SDCLKDLY
45
29
Reserved
Pin Configuration Register (PCFG)
input signal level and the corresponding register value are indicated.
R/W
For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial
00
Reserved
Reserved
DATA Signal
Control
CB Signal
Control
DQM Signal
Control
ADDR Signal
Control
CKE Signal
Control
RAS Signal
Control
CAS Signal
Control
44
28
Field Name
SYSCLKEN
DRVCK[3:0]
R/W
27
ADDR[5]
1
R/W
Figure 5.2.3 Pin Configuration Register (1/3)
26
10
Specifies the driving capability of the DATA[63:0] signals.
L : 0 = 8 mA
H : 1 = 16 mA
Specifies the driving capability of the CB[7:0]* signals.
L : 0 = 8 mA
H : 1 = 16 mA
Note: CB[7:0}* share pins with PIO[15:8], E0TXD[3:0],
Specifies the driving capability of the DQM[7:0]* signals.
L : 0 = 8 mA
H : 1 = 16 mA
Specifies the driving capability of the ADDR[19:0] signals.
L : 0 = 8 mA
H : 1 = 16 mA
Specifies the driving capability of the CKE signal.
L : 0 = 8 mA
H : 1 = 16 mA
Specifies the driving capability of the RAS* signal.
L : 0 = 8 mA
H : 1 = 16 mA
Specifies the driving capability of the CAS* signal.
L : 0 = 8 mA
H : 1 = 16 mA
SDCLKEN[3:0]
ADDR[9] ADDR[18]
SEL2
E0RXD[3:0].
The driving capability of these pins are below.
CB[7:0], E0TXD[3:0], E0RXD[3:0]: 8 mA or 16 mA
PIO[15:8]:
57
41
9
R
1111
R/W
DRVCKIN
DRVDATA
ADDR[4] ADDR[4] ADDR[4] ADDR[5] ADDR[5] ADDR[5] ADDR[5] ADDR[5] ADDR[5]
ADDR[5]
SEL1
R/W
R/W
56
40
R
8
DRVCB DRVDQM
R/W
55
39
23
DMASEL3
5-7
7
Description
R/W
00
SDCLKINEN
R/W
R/W
⎯
Chapter 5 Configuration Registers
54
22
0
DRVADDR
R/W
53
21
DMASEL2
0xE010
R/W
8 mA only
00
Reserved
DRVCKE DRVRAS DRVCAS DRVWE
R/W
52
PCICLKEN[5:0]
R/W
51
DMASEL1
111111
R/W
R/W
00
R/W
50
Initial Value Read/Write
ADDR[4]
ADDR[4]
ADDR[4]
ADDR[5]
ADDR[5]
ADDR[5]
ADDR[5]
⎯
R/W
49
33
DMASEL0
R/W
00
BYPASSPLL*
DRVCS[3]
BYPASSPLL
R/W : Type
48
32
16
R
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
⎯