TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 381

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

31:13
Bit
6:5
4:1
12
11
10
9
8
7
0
31
15
11.4.6
Reserved
Mnemonic
RTSSC
RTSTL
RSDE
TSDE
TBRK
RCS
TES
Flow Control Register 0 (SIFLCR0)
Flow Control Register 1 (SIFLCR1)
13
RCS
R/W
Reserved
RTS Signal
Control Select
CTS Signal
Control Select
Reserved
RTS Software
Control
Serial Data
Reception
Disable
Serial Data
Transmit Disable
Reserved
RTS Active
Trigger Level
Break
Transmission
12
0
Field Name
TES
R/W
11
0
Reserved
10
Figure 11.4.6 Flow Control Register
RTS Control Select (Default: 0)
This field sets the reception flow control using RTS output signals.
0: Disable flow control using RTS signals.
1: Enable flow control using RTS signals.
CTS Control Select (Default: 0)
This field sets the transmission flow control using CTS input signals.
0: Disable flow control using CTS signals.
1: Enable flow control using CTS signals.
RTS Software Control (Default: 0)
This register is used for software control of RTS output signals.
0: Set the RTS signal to Low (can receive data).
1: Sets the RTS signal to High (transmission pause request)
Receive Serial Data Disable (Default: 1)
This is the Serial Data Disable bit. When this bit is cleared, data reception
starts after the start bit is detected. The RTS signal will not become High
even if this bit is cleared.
0: Enable (can receive data)
1: Disable (halt reception)
Transmit Serial Data Disable (Default: 1)
This is the Serial Data Transmission Disable bit. When this bit is cleared,
data transmission starts. When set, transmission stops after completing
transmission of the current frame.
0: Enable (can transmit data)
1: Disable (halt transmission)
RTS Trigger Level (Default: 0001)
The RTS hardware control assert level is set by the reception data stage
count of the Receive FIFO.
0000: Disable setting
0001: 1
1111: 15
Break Transmit (Default: 0)
Transmits a break. The TXD signal is Low while TBRK is set to “1”.
0: Disable (clear break)
1: Enable (transmit break)
RTSSC
:
R/W
9
0
RSDE TSDE
R/W
Reserved
8
1
11-21
R/W
7
1
0xF314 (Ch. 0)
0xF414 (Ch. 1)
Reserved
6
Description
5
Chapter 11 Serial I/O Port
4
RTSTL
0001
R/W
1
TBRK
R/W : Type
16
Read/Write
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Type
: Initial value
: Initial value
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