TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 264

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

10.3.3
Note: The byte enable signals are asserted as necessary during memory read and memory
Key:
C/BE Value
Supported PCI Bus Commands
•
•
Table 10.3.1 shows the PCI Bus commands that the PCI Controller supports.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
I/O Read, I/O Write, Memory Read, Memory Write
Memory Read Multiple, Memory Read Line
the Initiator function is operating and Burst Read access is issued from the G-Bus to the PCI Bus.
(1) A value other than “0” is set to the Cache Line Size Field (PCICFG1.CLS) of the PCI
(2) The Read data word count is equal to or less than the value set in the Cache Line Size Field.
(1) A value other than “0” is set to the Cache Line Size Field (PCICFG1.CLS) of the PCI
(2) The Read data word count is equal to or less than the value set in the Cache Line Size Field.
This command executes Read/Write access to the address mapped on the G-Bus and PCI Bus.
The Memory Read Multiple command is issued if all of the following conditions are met when
write cycles using I/O Read, I/O Write and Single Access commands. During burst
memory reads, four byte enable signals are asserted.
√ : Supported when in both the Host mode and the Satellite mode
† : Supported only when in the Host mode
‡ : Supported only when in the Satellite mode
— : Not supported
Also, the Read Memory Line command is issued when all of the following conditions are met.
Configuration 1 Register.
Configuration 1 Register.
Memory Write and Invalidate
Table 10.3.1 Supported PCI Bus Commands
Memory Read Multiple
Interrupt Acknowledge
Dual Address Cycle
Configuration Read
Configuration Write
Memory Read Line
PCI Command
Memory Read
Memory Write
Special Cycle
(Reserved)
(Reserved)
(Reserved)
(Reserved)
I/O Read
I/O Write
10-6
As Initiator
⎯
⎯
⎯
⎯
Chapter 10 PCI Controller
†
†
√
√
√
√
†
†
√
√
√
√
As Target
⎯
⎯
⎯
⎯
⎯
⎯
√
√
√
√
‡
‡
√
√
√
√