TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 187

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

63:32
31:16
15:11
Bit
10
9
8.4.3
63
47
31
15
Mnemonic
STLXFER
CHNEN
WAITC
DMA Channel Status Register (DM0CSRn, DM1CSRn))
Reserved
Offset Address: DMAC0 0xB038 (ch. 0) / 0xB078 (ch. 1) / 0xB0B8 (ch. 2) / 0xB0F8 (ch. 3)
Reserved
Wait Counter
Reserved
Chain Enable
Transfer Stall
Detect
Field Name
Figure 8.4.3 DMA Channel Status Register (1/2)
DMAC1 0xB838 (ch. 0) / 0xB878 (ch. 1) / 0xB8B8 (ch. 2) / 0xB8F8 (ch. 3)
11
CHNEN
Wait Counter (Default: 0x0000)
This is a diagnostic function.
• I/O DMA transfer mode (DMCCRn.EXTRQ = “1”)
This counter is decremented by 1 at each 64 G-Bus cycles. After channel n
releases bus ownership, this counter sets the default (the value that is the
detection interval clock cycle count set by the Transfer Stall Detection
Interval field (DMCCRn.STLTIME) divided by 64). The Transfer Stall
Detect bit (DMCSRn.STLXFER) is set when the interval during which bus
ownership is not held reaches the set clock cycle. The counter is reset to
the default and stops counting. Clearing the Transfer Stall Detect bit
(DMCSRn.STLXFER) resumes the count and starts stall detection.
• Memory transfer mode (DMCCRn.EXTRQ = “0”)
This counter is decremented by 1 at each G-Bus cycle. After bus
ownership is released, the counter is set to the delay clock cycle count set
by the Internal Request Delay field (DMCCRn.INTRQD). When the counter
reaches “0” the count stops and channel n requests bus ownership.
Chain Enable (Default: 0)
This value is a copy of the Chain Enable bit (CHNEN) of the DMA Channel
Control Register (DMCCRn).
Stalled Transfer Detect (Default: 0)
This bit indicates whether the interval during which bus ownership is not
held exceeds the value set by the Transfer Stall Detect Interval field
(DMCCRn.STLTIME) after bus ownership is released when in the I/O DMA
transfer mode.
1: Indicates that the interval during which bus ownership was not held
0: The interval during which bus ownership was not held did not exceed
10
exceeds the DMCCRn.STLTIME setting.
the setting since this bit was last cleared.
R
0
R/W1C
STLXFER
9
0
XFACT ABCHC NCHNC
Reserved
Reserved
R
0
8
0x0000
WAITC
8-31
R
R
7
0
Description
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C : Type
6
0
NTRNFC
Chapter 8 DMA Controller
5
0
EXTDN CFERR CHERR
0
4
3
0
2
0
DESERR SORERR
1
0
Read/Write
R
R
R/W1C
48
32
16
0
0
⎯
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Initial value