TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 277

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Note: In the initiator write cycle, access on the G-Bus has been finished before access on the PCI
Negative Increase Burst Transfer Detect
Zero Increase Burst Transfer Detect
10.3.11.2 PDMAC Interrupts
10.3.11.3 Power Management Interrupts
10.3.11.4 Error Detection Interrupts
Normal Data Transfer Termination
Inter-Transfer Stall Time Reached
Long Burst Transfer Detect
Normal Chain Termination
PM Status Change Detect
PME Status Clear Detect
Master Data Parity Error
G-Bus Bus Error Detect
bus is finished (Post write). Therefore, when an error occurs on PCI bus, it is reported with an
error detection interrupt, as shown above.
In the initiator read cycle, when an error occurs on the PCI bus access, PCIC responds with a
G-Bus error instead of returning read data to the G-Bus. Setting "0" to the IRBER bit of the
PCICFG register suppresses output of a G-Bus error during initiator read.
Master Abort Receive
Broken Master Detect
Target Abort Receive
System Error Report
TRDY Timeout Error
PME_En Set Detect
Target Abort Report
Retry Timeout Error
Configuration Error
G-Bus Chain Error
Parity Error Detect
G-Bus Data Error
PCI Fatal Error
PERR* Detect
SERR* Detect
PME Detect
Name
Name
Name
/ PCISSTATUS
PCICSTATUS
PCICSTATUS
PDMSTATUS
P2GSTATUS
G2PSTATUS
PBASTATUS
PCISTATUS
10-19
Status Bit
Status Bit
Status Bit
DATAERR
CHNERR
CFGERR
PMECLR
PCIERR
NCCMP
STLTRF
IDTTOE
IDRTOE
NTCMP
PMEES
PMSC
MDPE
PERR
SERR
RMA
BMD
PME
DPE
SSE
GBE
RTA
STA
TLB
NIB
ZIB
Chapter 10 PCI Controller
PCICMASK
PCICMASK
P2GMASK
G2PMASK
PBAMASK
PCIMASK
PDMCFG
Interrupt Enable Bit
Interrupt Enable Bit
Interrupt Enable Bit
PMECLRIE
NCCMPIE
IDTTOEIE
IDRTOEIE
NTCMPIE
PMEESIE
PMSCIE
MDPEIE
PERRIE
SERRIE
RMAIE
BMDIE
ERRIE
PMEIE
GBEIE
DPEIE
SSEIE
RTAIE
STAIE
TLBIE
NIBIE
ZIBIE