TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 62

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Signal Name
Signal Name
TCK
TDI/DINT*
TDO/TPC[0]
TPC[3:1]
TMS
TRST*
DCLK
PCST[8:0]
MASTERCLK
HALTDOZE
BYPASSPLL*
CGRESET*
3.1.11
3.1.12
Extended EJTAG Interface Signals
Clock Signals
Output
Output
Output
Output
Output
Type
Type
Input
Input
Input
Input
Input
Input
Input
PU
PU
PU
JTAG Test Clock Input
Clock input signal for JTAG.
TCK is used to execute JTAG instructions and input/output data.
JTAG Test Data Input/Debug Interrupt
When PC trace mode is not selected, this signal is a JTAG data input signal. It is used to
input serial data to JTAG data/instruction registers.
When PC trace mode is selected, this signal is an interrupt input signal used to cancel
PC trace mode for the debug unit.
JTAG Test Data Output/PC Trace Output
When PC trace mode is not selected, this signal is a JTAG data output signal. Data is
output by means of serial scan.
When PC trace mode is selected, this signal outputs the value of the non-continuous
program counter in sync with the debug clock (DCLK).
PC Trace Output
TPC[3:1] output the value of the noncontiguous program counter in sync with DCLK.
These signals are common with the other functions (refer to Section “3.3 Pin multiplex”).
Use the configuration setting during boot-up.
JTAG Test Mode Select Input
TMS mainly controls state transition in the TAP controller state machine.
Test Reset Input
Asynchronous reset input for the TAP controller and debug support unit (DSU).
TRST* pin must be pulled down (ex.10 kΩ).
When this signal is deasserted, G-Bus timeout detection is disabled (refer to Section
“5.1.1 Detecting G-Bus Timeout”).
Debug Clock
Clock output signal for the real-time debugging system.
When PC trace mode is selected, the TPC[3:1] and PCST signals are output
synchronously. This clock is the TX49/H3 core operating clock (CPUCLK) divided by 3.
This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use
the configuration setting during boot-up.
PC Trace Status Information
Outputs PC trace status and other information.
These signals are common with the other functions (refer to Section “3.3 Pin multiplex”).
Use the configuration setting during boot-up.
Master Clock
Input pin for the TX4937 operating clock. A crystal resonator cannot be connected to this
pin because the pin does not contain an oscillator.
Halt/Doze State Output
This signal is asserted (High output) when the TX4937 enters Halt or Doze mode.
Bypass PLL
This pin must be fixed to High.
CG Reset
CGRESET* initializes the CG.
Table 3.1.11 Extended EJTAG Interface Signals
Table 3.1.12 Clock Signals
3-8
Description
Description
Chapter 3 Signals
Initial State
Initial State
Input
Input
High
All High
Input
Input
Low
All Low
Input
Low
Input
Input