TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 285

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

R/W1C R/W1C R/W1C R/W1C R/W1C
26:25
DPE
Bit
31
30
29
28
27
31
15
0
10.4.2
Mnemonic
SSE
30
0
correspond to the Command Register in the PCI Configuration Space.
the upper 16 bits from the Satellite Mode PCI Status Register (PCISSTATUS).
RMA
DPE
SSE
RTA
STA
DT
The upper 16 bits correspond to the Status Register in the PCI Configuration Space, and the lower 16 bits
This register cannot be accessed when in the Satellite mode. However, it is possible to read some values of
RMA
PCI Status, Command Register (PCISTATUS)
29
Reserved
0
Detected Parity
Error
Signaled System
Error
Received Master
Abort
Received Target
Abort
Signaled Target
Abort
DEVSEL Timing
RTA
Field Name
28
0
STA
27
0
Figure 10.4.2 PCI Status, Command Register (1/3)
26
10
Detected Parity Error (Default: 0)
Indicates that a parity error was detected. A parity error is detected in the
three following situtations:
• Detected a data parity error as the Read command PCI initiator.
• Detected a data parity error as the Write command PCI target.
• Detected an address parity error.
This bit is set regardless of the setting of the Parity Error Response bit
(PCISTATUS.PEREN) of the PCI Status, Command Register.
1: Detected a parity error.
0: Did not detect a parity error.
Signaled System Error (Default: 0)
Detects either an address parity error or a special cycle data parity error.
This bit is set when the SERR* signal is asserted.
1: Asserted the SERR* signal
0: Did not assert the SERR* signal.
Received Master Abort (Default: 0)
This bit is set when a Master Abort aborts a PCI Bus Transaction when the
PCI Controller operates as the PCI initiator (except for special cycles).
1: Transaction was aborted by a Master Abort.
0: Transaction was not aborted by a Master Abort.
Received Target Abort (Default: 0)
This bit is set when a Target Abort aborts a PCI Bus Transaction when the
PCI Controller operates as the PCI initiator.
1: Transaction was aborted by a Target Abort.
0: Transaction was not aborted by a Target Abort.
Signaled Target Abort (Default: 0)
This bit is set when a Target Abort aborts a PCI Bus Transaction when the
PCI Controller operates as the PCI target.
1: Bus transaction was aborted by a Target Abort.
0: Bus transaction was not aborted by a Target Abort.
DEVSEL Timing (Fixed Value: 01)
Three DEVSEL assert timings are defined in the PCI 2.2 Specifications:
00b = Fast; 01b = Medium; 10b = Slow; 11b = Reserved).
With the exception of Read Configuration and Write Configuration, when
the PCI Controller is the PCI target, the DEVSEL signal is asserted to a
certain bus command and indicates the slowest speed for responding to
the PCI Bus Master.
DT
01
R
FBBEN SEREN STPC PEREN VPS MWIEN
R/W
25
9
0
R/W1C
MDPE FBBCP
R/W
24
0
8
0
10-27
23
R
R
1
7
0
Reserved
R/W
22
Description
6
0
66MCP
21
R
R
1
5
0
Chapter 10 PCI Controller
0xD004
R/W
CL
20
R
1
4
0
SC
19
0
R
3
R/W
BM
0/1
Reserved
2
MEMSP
R/W
1
0
IOSP
Read/Write
R/W : Type
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R
16
0
0
: Type
: Initial value
: Initial value