TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 353

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

63:30
29:24
23:20
19:18
17:16
15:12
Bit
11
10
63
47
31
15
Reserved
9
10.4.63 PDMAC Status Register (PDMSTATUS)
Mnemonic
DONEINT
30
REQCNT
FIFOCNT
Reserved
FIFOWP
ERRINT
FIFORP
CHNEN
29
Reserved
Request Delay
Time Counter
FIFO Hold Count
FIFO Write
Pointer
FIFO Read
Pointer
Reserved
Error Interrupt
Status
Normal Transfer
Complete
Interrupt Status
Chain Enable
Field Name
12
ERRINT
0x0
11
REQCNT
R
0x00
R
DONEINT
0x0
10
R
Request Delay Counter (Default: 0x00)
This field indicates the request delay time counter value as 16 × n when the
6-bit value of this field is n.
FIFO Valid Entry Count (Default: 0x0)
This field indicates the number of bytes that was written in the FIFO but not
yet read. This is a diagnostic function.
FIFO Write Pointer (Default: 0x0)
This field indicates the next Write position in the FIFO. This is a diagnostic
function.
FIFO Read Pointer (Default: 0x0)
This field indicates the next Read position in the FIFO. This is a dianostic
function.
Error Interrupt Status (Default: 0x0)
Indicates whether to signal an error interrupt.
1: An error interrupt request exists.
0: No error interrupt request exists.
Normal Transfer Complete Interrupt Status (Default: 0x0)
Indicates whether a Normal Transfer Complete Interrupt is signaled.
This bit becomes “1” when either the Normal Chain Complete bit (NCCMP)
is set and the Normal Chain Complete Interrupt Enable bit (NCCMPIE) is
set, or when the Normal Data Transfer Complete bit (NTCMP) is set and
the Normal Data Transfer Complete Interrupt Enable bit (NTCMPIE) is set.
1: A Normal Transfer Complete Interrupt request exists.
0: No Normal Transfer Complete Interrupt request exists.
Chain Enable (Default: 0x0)
This bit is a copy of the Chain Enable bit in the PDMAC Configuration
Register.
Figure 10.4.61 Status Register (1/2)
CHNEN
0x0
R
9
XFRACT
0x0
24
Reserved
Reserved
R
8
10-95
ACCMP NCCMP NTCMP
0x0
23
R
7
R/W1C R/W1C
0x0
FIFOCNT
Description
6
0x0
R
0x0
5
Chapter 10 PCI Controller
0xD228
Reserved
20
4
R/W1C R/W1C R/W1C R/W1C : Type
CFGERR
0x0
19
FIFOWP
3
0x0
R
PCIERR
0x0
18
2
CHNERR
0x0
17
1
FIFORP
0x0
R
DATAERR
Read/Write
R
R
R
R
R
R
R
0x0
48
32
16
0
⎯
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Initial value