TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 305

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TMPR4937XBG-300

Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPR4937XBG-300

Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPR4937XBG-300
Manufacturer:
TOSHIBA
Quantity:
16 845
Part Number:
TMPR4937XBG-300
Manufacturer:
DSP
Quantity:
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31:25
20:0
Bit
24
23
22
21
31
15
10.4.21 P2G Interrupt Mask Register (P2GMASK) 0xD098
Mnemonic
PMECLRIE
PMEESIE
M66ENIE
PMSCIE
Reserved
Reserved
Power
Management
State Change
Interrupt Enable
PME_En Set
Interrupt Enable
PME Status Clear
Interrupt Enable
66 MHz Drive
Interrupt Enable
Reseved
Field Name
Figure 10.4.19 P2G Interrupt Mask Register
Power Management State Change Interrupt Enable (Default: 0x0)
Generates an interrupt when the PowerState field of the Power
Management Register (PMCSR) is rewritten.
1: Generates an interrupt.
0: Does not generate an interrupt.
PME_En Set Interrupt Enable (Default: 0x0)
Generates an interrupt when the PME_En bit of the PMCSR Register is
set.
1: Generates an interrupt.
0: Does not generate an interrupt.
PME_Status Clear Interrupt Enable (Default: 0x0)
Generates an interrupt when the PME_Status bit of the PMCSR Register is
cleared.
1: Generates an interrupt.
0: Does not generate an interrupt.
M66EN Detected Interrupt Enable (Default: 0x0)
Generates an M66EN interrupt when the PCI Controller is in the Satellite
mode.
Note: This bit must be masked in order to clear an M66EN interrupt since
1: Generates an interrupt.
0: Does not generate an interrupt.
the M66EN bit of the P2GSTATUS Register itself cannot be cleared.
When the PCI Controller is in the Host mode, M66EN interrupts are
invalid and will not be signaled even if this bit is set to “1”.
25
PMSCIE
R/W
0x0
24
Reserved
10-47
PMEESIE
R/W
0x0
23
PMECLRIE
R/W
0x0
22
Description
M66ENIE
R/W
0x0
21
Chapter 10 PCI Controller
20
Reserved
Read/Write
R/W
R/W
R/W
R/W
16
0
: Type
: Initial value
: Type
: Initial value

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