TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 427

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Bit
7:5
13
12
11
10
9
8
4
3
2
1
0
Mnemonic
DMA and to stop transmission/reception by the AC-link. Note that if these bits are cleared while
output-slot data is flowing in the FIFO, ACLC may output a wrong data as the last sample. This
behavior will not occur if the software waits for data-flow completion by detecting underrun before it
disables the corresponding slot.
Clear xxxxDMA bits in ACCTLEN to “0” by using this register to disable transmit/receive-data
Reserved
Reserved
Field Name
—
—
—
—
—
—
—
—
—
—
AUDIDMA: Disable Audio Receive-data DMA.
LFEDMA: Disable Audio LFE Transmit-data DMA.
CENTDMA: Disable Audio Center Transmit-data DMA.
SURRDMA: Disable Audio Surround L&R Transmit-data DMA.
AUDODMA: Disable Audio PCM L&R Transmit-data DMA.
MICSEL: MIC Selection
WRESET: Deassert Warm Reset.
WAKEUP: Disable Wake-up.
LOWPWR: Disable AC-link Low-power Mode.
ENLINK: Disable AC-link.
Figure 14.4.2 ACCTLDIS Register (2/2)
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
0: No effect
1: Disables audio receive-data DMA.
0: No effect
1: Disables audio LFE transmit-data DMA.
0: No effect
1: Disables audio Center transmit-data DMA.
0: No effect
1: Disables audio Surround L&R transmit-data DMA.
0: No effect
1: Disables audio PCM L&R transmit-data DMA.
0: No effect
1: Selects PCM L&R (Slot 3&4) for audio reception
0: No effect
1: Deasserts warm reset.
[Note: The software must guarantee the warm reset assertion
0: No effect
1: Disables wake-up from low-power mode.
0: No effect
1: Releases SYNC and SDOUT signals from low.
0: No effect
1: Asserts the ACRESET* signal to AC-link.
[Note: The software must guarantee the ACRESET* signal
time meets the AC’97 specification (1.0 µs or more).]
assertion time meets the AC’97 specification (1.0 µs or
more).]
14-21
Description
Chapter 14 AC-link Controller
Read/Write
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
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