TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 116
TMPR4937XBG-300
Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet
1.TMPR4937XBG-300.pdf
(552 pages)
Specifications of TMPR4937XBG-300
Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant
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ACK*/READY (Input)
SWE*/BWE*
ADDR [19:0]
DATA [31:0]
7.3.7.4
ACK*/READY (Input)
SYSCLK
CE*
ADDR [19:0]
DATA [31:0]
ACK* Input Timing (External ACK Mode)
acknowledged (Figure 7.3.9 ACK* Input Timing (Single Read Cycle)). During a Write cycle,
assertion of the ACK* signal is acknowledged, SWE*/BWE* is deasserted three clock cycles
later, then data is held for one clock cycle after that (Figure 7.3.10 ACK* Input Timing (Single
Write Cycle).
ACK* cannot be acknowledged consecutively on consecutive clock cycles. External devices can
assert ACK* across multiple clock cycles under the following conditions.
•
•
SYSCLK
The ACK* signal becomes an input signal when in the external ACK mode.
During a Read cycle, data is latched two clock cycles after assertion of the ACK* signal is
The ACK* input signal is internally synchronized. Due to internal State Machine restrictions,
OE*
CE*
During Single access, the ACK* signal can be asserted before the end of the cycle during
which CE* is dasserted.
During Burst access, it is possible to assert the ACK* signal for up to three clock cycles
during Reads and for up to five clock cycles during Writes. If the ACK* signal is asserted for
a period longer than this, it will be acknowledged as the next valid ACK* signal.
Figure 7.3.10 ACK* Input Timing (Single Write Cycle)
Figure 7.3.9 ACK* Input Timing (Single Read Cycle)
Acknowledge ACK*
7-16
Acknowledge ACK*
Chapter 7 External Bus Controller
3 clocks
2 clocks
4 clocks
Latch Data
EBCCRn.SHWT=0
EBCCRn.SHWT=0
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