TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 354

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Bit
8
7
6
5
4
3
2
1
0
Mnemonic
DATAERR
CFGERR
CHNERR
XFRACT
PCIERR
ACCMP
NCCMP
NTCMP
Transfer Active
Abnormal Chain
Completion
Normal Chain
Completion
Normal Data
Transfer
Complete
Reserved
Configuration
Error
PCI Fatal Error
G-Bus Chain
Error
G-Bus Data Error
Field Name
Transfer Active (Default: 0x0)
This bit is a copy of the Transfer Active bit in the PDMAC Configuration
Register.
Abnormal Chain Complete (Default: 0x0)
1: Indicates that the Chain transfer ended in an error state. In other words,
0: Indicates that no error has occurred in the Chain transfer since the
Note: Bits [3:0] of the PDMAC Status Register must be cleared in order to
Normal Chain Complete (Default: 0x0)
1: Indicates that the Chain transfer ended in the Normal state.
0: Indicates that Chain transfer has not ended since this bit was previously
cleared.
Normal Data Transfer Complete (Default: 0x0)
1: Indicates that the data transfer specified by the PDMAC Register ended
0: Indicates that data transfer has not ended since this bit was previously
Configuration Error (Default: 0x0)
1: Indicates that either the current setting of the control portion in the
0: Indicates that the current setting of the control portion in the Control
PCI Fatal Error (Default: 0x0)
1: Indicates that an error was signaled on the PCI Bus during the Chain
0: Indicates that no error has been signaled on the PCI Bus since this bit
G-Bus Chain Bus Error (Default: 0x0)
1: Indicates that a G-Bus error occurrred during the Chain process. DMA
0: Indicates that no G-Bus error has occurred during the Chain process
G-Bus Data Bus Error (Default: 0x0)
1: Indicates that a G-Bus error occurred during the data transfer process.
0: Indicates that no G-Bus error has occurred during the data transfer
Figure 10.4.61 Status Register (2/2)
this reflects an OR operation of the PDMAC Status Register bits [3:0].
previous error bit was cleared.
in the Normal state.
cleared.
Control Register and the Address/Count Register are not consistent with
each other or the PDMAC stipulation is not being obeyed. DMA transfer
stops.
Register can be tolerated.
process.
was previously cleared.
transfer stops.
since this bit was cleared.
DMA transfer stops.
process since this bit was cleared.
clear this bit.
10-96
Description
Chapter 10 PCI Controller
Read/Write
R
R
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
⎯