TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 395

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

31:4
Bit
31
15
3
2
1
0
12.4.2
Mnemonic
TPIBS
TPIAS
TWIS
TIIS
Timer Interrupt Status Register n (TMTISRn)
Reserved
Watchdog Timer
Status
Pulse Generator
TMCPRB Status
Pulse Generator
TMCPRA Status
Interval Timer
TMCPRA Status
Field Name
Figure 12.4.2 Timer Interrupt Status Register
Reserved
Watchdog Timer TMCPRA Match Status (Default: 0)
(This bit is Reserved in the case of the TMTISR0 Register and the TMTISR1
Register.)
When in the Watchdog Timer mode, this bit is set when the counter value
matches Compare Register 2 (TMCPRA2).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Negate interrupt
1: Invalid
Pulse Generator TMCPRB Match Status (Default: 0)
(This bit is Reserved in the case of the TMTISR2 Register.)
When in the Pulse Generator mode, this bit is set when the counter value
matches Compare Register Bn (TMCPRBn).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
Pulse Generator TMCPRA Match Status (Default: 0)
(This bit is Reserved in the case of the TMTISR2 Register.)
When in the Pulse Generator mode, this bit is set when the counter value
matches Compare Register A n (TMCPRAn).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
Interval Timer TMCPRA Match Status (Default: 0)
When in the Interval Timer mode, this bit is set when the counter value
matches Compare Register A n (TMCPRAn).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
Reserved
12-11
Description
TMTISR0
TMTISR1
TMTISR2
Chapter 12 Timer/Counter
4
RW0C RW0C RW0C RW0C : Type
TWIS TPIBS TPIAS
3
0
0xF004
0xF104
0xF204
2
0
1
0
Read/Write
R/W0C
R/W0C
R/W0C
R/W0C
TIIS
16
0
0
⎯
: Type
: Initial value
: Initial value