TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 280

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

10.3.13 PCI Boot
10.3.12.5 Special Programming
vector address of the TX49/H3 core to PCI Bus address 0x00_BFC0_0000.
Boot mode. The defaults of several registers are changed as indicated below.
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Satellite mode.
Setting the configuration during boot up (ADDR[8:6]) makes it possible to set the reset exception
Two windows of the memory space from the G-Bus to the PCI Bus space are used when in the PCI
Also, the on-chip PCI Bus Arbiter cannot be used when the PCI Boot mode is being used while in the
G-Bus base address (G2GBASE):
Space size (G2PM2MASK):
PCI Bus base address (G2PM2PBASE):
Initiator Memory Space 2 Enable (PCICCFG.G2PM2EN):
Bus Master bit (PCISTATUS.BM) [Only when in the Host mode]
Target Configuration Access Ready
(PCICSTAUTS.TCAR) [Only when in the Satellite mode]
devices. PCI devices with the following characteristics can be made usable by changing the
programming of the PCI bus arbiter.
1.
2.
PCI bus arbiter as follows:
to be written to the PBACFG and PBAREQPORT registers are as follows:
There may be some devices among PCI bus masters that operate differently from typical PCI
For example, a bus master with both of the above characteristics can be used by configuring the
If this bus master is connected to REQ[3] and broken master checking is to be enabled, values
Bus masters that can not re-assert REQ unless GNT is once deasserted after deasserting REQ
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Bus masters that initiate a PCI transaction even when the deassertion of GNT has taken away
their bus mastership before the start of the transaction
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Assign the bus master to a request port other than Port A through the PBAREQPORT
register (at 0xD100). (Assign the TX4937 to Port A.)
Enable the Fixed Parked Master (FIXPA) bit in the PBACFG register (at 0xD104).
Assign the bus master to request port A, B, C or D through the PBAREQPORT register
(at 0xD100).
Set the internal PCI bus arbiter to the fixed parked master.
Assign the TX4937 to request port A.
Assign the bus master to request port B.
PBACFG (at 0xD104):
PBAREQPORT (at 0xD100): 0x73546210
10-22
0x0000000B
Chapter 10 PCI Controller
0x0_1FC0_0000
4 MB
0x00_BFC0_0000
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